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Core8051
Core Verification
? Comprehensive VHDL and Verilog Testbenches
? Users Can Easily Add Custom Tests by Modifying
the User Testbench Using the Existing Format
Contents
General Description .................................................... 2
Core8051 Device Requirements ................................. 4
Core8051 Verification ................................................ 5
I/O Signal Descriptions ............................................... 5
Memory Organization ................................................ 8
Special Function Registers ........................................ 10
Instruction Set ........................................................... 11
MUL and DIV instructions. Furthermore, each cycle in the
8051 used two memory fetches. In many cases, the second
fetch was a "dummy" fetch and extra clocks were wasted.
Table 1 shows the speed advantage of Core8051 over the
standard 8051. A speed advantage of 12 in the first
column means that Core8051 performs the same
instruction 12 times faster than the standard 8051. The
second column in Table 1 lists the number of types of
instructions that have the given speed advantage. The
third column lists the total number of instructions that
have the given speed advantage. The third column can be
thought of as a subcategory of the second column. For
example, there are two types of instructions that have a
three-time speed advantage over the classic 8051, for
which there are nine explicit instructions.
Table 1 ? Core8051 Speed Advantage Summary
Instruction Definitions ............................................. 19
Instruction Timing .................................................... 20
Core8051 Engine ...................................................... 27
Timers/Counters ........................................................ 28
Serial Interface .......................................................... 30
Interrupt Service Routine Unit ................................. 32
ISR Structure ............................................................. 35
Power Management Unit ........................................ 36
Power Management Implementation ..................... 36
Interface for On-Chip Instrumentation (Optional) . 37
Ordering Information .............................................. 39
List of Changes ......................................................... 40
Datasheet Categories ............................................... 40
Speed
Advantage
24
12
9.6
8
6
4.8
4
3
Average: 8.0
Number of
Instruction
Types
1
27
2
16
44
1
18
2
Sum: 111
Number of
Instructions
(Opcodes)
1
83
2
38
89
2
31
9
Sum: 255
The average speed advantage is 8.0. However, the real
speed improvement seen in any system will depend on the
General Description
The Core8051 macro is a high-performance, single-chip, 8-
bit microcontroller. It is a fully functional eight-bit
embedded controller that executes all ASM51 instructions
and has the same instruction set as the 80C31. Core8051
instruction mix.
Core8051 consists of the following primary blocks:
? Memory Control Block – Logic that Controls
Program and Data Memory
? Control Processor Block – Main Controller Logic
provides software and hardware interrupts, a serial port,
and two timers.
The Core8051 architecture eliminates redundant bus
states and implements parallel execution of fetch and
execution phases. Since a cycle is aligned with memory
fetch when possible, most of the one-byte instructions are
performed in a single cycle. Core8051 uses one clock per
cycle. This leads to an average performance improvement
rate of 8.0 (in terms of MIPS) with respect to the Intel
device working with the same clock frequency.
The original 8051 had a 12-clock architecture. A machine
cycle needed 12 clocks, and most instructions were either
one or two machine cycles. Therefore, the 8051 used
either 12 or 24 clocks for each instruction, except for the
2
v6.0
?
?
?
?
?
?
?
?
?
?
RAM and SFR Control Block
ALU – Arithmetic Logic Unit
Reset Control Block – Provides Reset Condition
Circuitry
Clock Control Block
Timer 0 and 1 Block
ISR – Interrupt Service Routine Block
Serial Port Block
Port Registers Block
PMU – Power Management Unit Block
OCI block – On-Chip Instrumentation Logic for
Debug Capabilities
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相关代理商/技术参数
CORE8051-EV 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051
CORE8051-SN 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051
CORE8051-SR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051
CORE8051-UR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051
CORE8051-XX 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Core8051
Core8b/10b-AR 制造商:Microsemi Corporation 功能描述:CORE - Virtual or Non-Physical Inventory (Software & Literature)
COREAES128 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreAES128
COREAES128-AN 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreAES128